1. Field of the Invention
This invention relates generally to the manufacture of high performance semiconductor devices and, more particularly, to the manufacture of high performance sub micron semiconductor devices and, even more particularly, to the manufacture of sub-half micron n-channel CMOS logic devices with improved current drive and reduced reverse short-channel effects.
2. Discussion of the Related Art
To achieve the higher performance required by end users of semiconductors, such as computer users, it is necessary for the semiconductor manufacturers to provide faster and smaller integrated circuits in faster chips. In addition, end users of semiconductors have demanded more functions on smaller chips. This, for example, has resulted in the requirement to increase the density of transistors on chips on each new generation of semiconductors.
Two of the major goals of MOSFET scaling are to increase the density and the speed of the integrated circuits in which the scaled-down devices are to be used. To increase density the physical dimensions have to be reduced which means smaller channel lengths and widths. To increase the speed of the integrated circuits, the MOSFET saturation drain current I.sub.DSAT must be increased to allow faster charging and discharging of parasitic capacitances. The long-channel MOSFET models derived for the pre-submicron long-channel MOSFETs predict that I.sub.DSAT should continue to increase with a decrease in either the channel length L or the gate oxide thickness t.sub.ox. The long-channel MOSFET models predict that I.sub.DSAT should continue to increase indefinitely as L and t.sub.ox are decreased, seeming to imply that only the limitations of process technology, i.e., not device effects, prevent the manufacture of smaller, higher-performing MOSFETs.
However, as process technology improved to the point where devices could be fabricated with gate lengths smaller than approximately 2 .mu.m, MOSFETs began to exhibit phenomena not predicted by the long-channel MOSFET models. Such phenomena are called "short-channel effects." One such unpredicted phenomena is the effect of gate dimensions on threshold voltage V.sub.T. There are three basic short-channel effects on the threshold voltage of MOSFETs: (1) the short-channel threshold-voltage shift; (2) narrow gate width effects on threshold voltage; and (3) the reverse short-channel threshold voltage shift.
It has been found that as the channel length dimension L is reduced to less than 2 .mu.m the difference between the predicted threshold voltage of MOSFETs and the actual measured threshold becomes significant. Typically, the threshold voltage V.sub.T decreases as L is reduced. However, in some situations it has been found that threshold voltage V.sub.T initially increases with decreasing channel length, beginning at about L=2-3 .mu.m, contrary to what would be predicted. This phenomenon is called "reverse short channel effect" (RSCE), "V.sub.T roll-up," or "anomalous threshold behavior." After V.sub.T reaches a maximum value due to RSCE, at about 0.7 .mu.m, V.sub.T declines as channel lengths are further decreased. This decline is called "V.sub.T roll off." It is theorized that the two-dimensional effects that are responsible for V.sub.T roll off eventually overcome the effects causing V.sub.T roll-up and dominate at the shorter channel lengths. In fact, another observed unexplained short channel phenomenon is that the rate of V.sub.T roll off with shorter L.sub.eff (effective channel length) is much faster than can be explained by the conventional models of laterally uniform channel doping. FIG. 1 illustrates the observed characteristics of the reverse short-channel effects on threshold voltage. The characteristic curve represented by 10 shows the region of roll-up at 12 and roll off at 14. The characteristic curve represented by 16 illustrates the expected decrease in threshold voltage V.sub.T with decreased channel length. The difference between the value represented by line 18 and the curve 10 is represented by delta V.sub.T. There have been different explanations for the roll-up effect, however, while several of the models seem to provide good quantitative agreement with experimental observations of the reverse short-channel effect, a consensus has not been achieved as to the cause of the reverse short-channel effect. The following models have been proposed as explanations of the reverse short-channel effect.
The first model proposes that the reverse short-channel effect is due to lateral dopant nonuniformity at the channel Si--SiO.sub.2 interface arising from enhanced diffusion of channel dopants caused by interstitial injection during poly reoxidation, salicide formation, or implant damage. This model was based on the fact that this effect was initially observed in nMOSFETs fabricated with two boron channel implants, a shallow boron implant for adjustment of the threshold voltage and a deeper boron implant for suppression of punchthrough. After the polysilicon gate is defined by etching and the source/drain regions are implanted, the thermal oxidation step (re-ox) is performed for several purposes, one of which is to reoxidize the source/drain regions. However, the reoxidation step also detrimentally impacts the V.sub.T characteristic of MOSFETs which employ lightly-doped drains (LDD). Therefore, the reoxidation step must be optimized for this type of device. The injection of interstitials which accompanies thermal oxidation causes oxidation-enhanced-diffusion (OED) of dopants in the vicinity of the growing oxide. This diffusion of dopants is enhanced not only under the oxidizing regions, (the source/drain regions) but also in the adjacent channel region due to lateral diffusion of the injection Si self-interstitials into the channel region. The oxidation-enhanced-diffusion causes boron to diffuse more rapidly which brings more boron from the deep buried peak concentration level to the surface near the edges of the channel. As a result, the boron surface concentration becomes larger at the channel edges which gives rise to an overall increase in V.sub.T if the channel length L becomes small enough to make these regions a significant fraction of the channel length. The V.sub.T roll-up has also been observed in MOSFETs in which a salicide is formed on the source/drain regions to reduce the sheet resistance of the source and drain. It has been suggested that during the silicide formation vacancies are injected and these enhance the dopant diffusion of the boron in the dual-implant profile. This also gives rise to a lateral nonuniform lateral distribution of boron along the channel surface. Similar to the oxidation-enhanced-diffusion model, this would increase V.sub.T as the MOSFET channel length is decreased.
Another proposed explanation is a model which suggests that the reverse short-channel effect arises from boron segregation to implant damaged regions at the edge of the channel. The first model discussed above does not explain the observation that V.sub.T roll-up occurs in MOSFETs with uniformly doped channel regions. The above models would predict that boron surface concentrations would decrease near the edges of the channels and thus V.sub.T would decrease monotonically with decreasing channel length in MOSFETs uniform channel regions. Because of the shortcoming of the above model, this model suggests another phenomenon as being responsible for the reverse short-channel effect roll-up and the subsequent enhanced roll-off effects as the channel length is decreased. This other phenomenon is that the reverse short-channel effect is caused by the depletion of boron from the channel region by strong segregation of the boron into the adjacent source and drain regions during the source/drain implant-activation anneal. This segregation is thought to occur as a result of the presence of crystal defects caused by the source/drain implant step. It is theorized that the boron has a higher local solubility in the defective regions and will diffuse to them during the anneal steps performed after the source/drain implant.
A further model attributes the reverse short-channel effect to transient enhanced diffusion of channel dopants to the silicon surface arising from implant damage. This model proposes that the effect is associated with damage from the LDD implant, i.e., that the point defects (interstitials) are assumed to be created by the LDD implant which diffuse laterally into the channel region during the relatively low-temperature step used to deposit the CVD interlevel dielectric layer needed to create the gate-sidewall spacers. As these point defects are primarily created at a depth corresponding to the end-of-range damage, the interstitial concentration peak would exist beneath the surface and, thus, a retrograde profile of interstitials in the channel will arise. Since the dopant diffusivity is proportional to the interstitial concentration, the retrograde interstitial concentration profile will cause a net boron diffusion flux toward the surface even if a flat boron dopant profile exists in the vertical direction. This would result in an increase of V.sub.T. The diffusion of boron toward the channel surface from this effect would be a transient phenomenon because the interstitials are eventually annihilated during the anneal.
Although the above models each provides a proposed theory of the cause of the reverse short-channel effect, none of them provides a solution that satisfactorily solves or decreases the reverse short-channel effect in all cases. What is needed is a device or method to reduce the reverse short-channel effect reliably and consistently.
Therefore, in the present invention, high arsenic doses are used to lower LDD (lightly doped drain) source/drain series resistance and a light phosphorus LDD dose is used to improve the hot carrier reliability in an nLDD structure and reduce the reverse short-channel effect. The shallow nLDD junctions are formed by implanting As and P at low energies. The resulting structure is a high-performance 0.20 .mu.m channel length CMOS logic technology operating at 2.9 V.